Verification is becoming an increasingly more critical phase of IC development.
ASIC verification takes as much as 70 percent of the ASIC development time and resources.
Verification problems are growing exponentially with every new design as complexity Increases.
More and more 'design' time is now spent 'verifying' to ensure First Time Right functionality.
Verification influences the cost, risk, available resources and degree of confidence in the design.

Dvita provides thorough and methodical Verification for ASIC and FPGA designs.
Comprehensive verification solutions are supplied to meet your testing requirements and achieve maximum coverage.
Dvita’s engineers have extensive experience in the leading EDA verification tools (such as Vera and Specman) and most popular test automation tools (such as Fastscan and Tetramax).
 
Dvita provides the following verification services
  • Create the Verification plan for your design
  • Generate Bus Functional Models
  • Generate Stimuli and Checkers
  • Implement Application Specific Test Suites
  • Develop and Verify Models for your RTL design
  • Develop and Verify Models for System component Blocks
Verification Languages
  • Specman, Vera, SystemC
Dvita provides the following Test services
  • Generate Functional Vectors, Memory Bist Vectors, Boundary Scan
  • Generate and validate Test Vectors for different Test equipment (ATPG)
  • Provide AC/DC parameter coverage
  • Provide Test vector coverage
 
Dvita, Inc., 1313 N. Milpitas Blvd, Suite 165, Milpitas, CA 95035. USA Designed & Developed by